1. Field of the Invention
The present invention relates to a digital phase alignment apparatus. More particularly, the present invention relates to a digital phase alignment apparatus in consideration of metastability which detects a rising transition or a falling transition of external input data, generates clock selecting signals using a resolving circuit which uses external input data used as a clock, limits activated clock selecting signal to one, and synthesizes generated clock selecting signals for retiming the external input data stably.
2. Description of the Prior Art
Generally, there exists a jitter occurred by a change of a time and temperature, and a static skew occurred by a delay difference of data bits and a retiming clock in a binary data bit transmitted in a high-speed. Particularly, a high-speed digital data transmitting system is often in the case that an overall system operates by being synchronous to a system clock. In this case, if the phase between a data and a clock doesn't separate enough to satisfy a setup time and hold time of a flip-flop, it is impossible to retime data stably according as a metastability condition happens.
FIG. 1 is a constructional view of a conventional high-speed digital retiming apparatus(application number: 95-50868).
As shown in FIG. 1, the conventional high-speed digital data retiming apparatus comprises a multiple phase clock generator 101, a clock selection signal generator 102, a synthetic clock generator 103, a retiming apparatus 104, and a buffer 105.
There will be explained an operation of a conventional high-speed digital data retiming apparatus constructed as above as follows:
First, the multi-phase clock generator 101 generates the n multi-phase clocks having the n phases. The clock selection signal generator 102 outputs a clock selection signal for selecting more than one clocks among the n number of multi-phase clocks whose a transition occurs in close vicinity to a center of a data unit interval entered from an external.
The synthetic clock generator 103 synthesizes clocks so that a transition of a clock can occur in the center of a data unit interval of an external according to a clock selection signal generated in the clock selection signal generator 102. The retimer 104 retimes the external data according to a clock synthesized in the synthetic clock generator 103. The retimed data of the retimer 104 is buffering according to the external clock through a buffer 105.
In such as a conventional high-speed digital data retiming apparatus, the phase difference between a first and n.sup.th clock of the n multi-phase clocks having the n number of phases generated from n/2 delay devices (n is natural number) can become the m period of the clock in compliance with a change of a derating factor according to the operating condition.
If the phase difference between a first and n.sup.th clock among the n multi-phase clocks is the m period, the selection signal number generated from the clock selection signal generator 103 is m, as a result, there can be used m clocks for producing a synthetic clock from the synthetic clock generator 103.
In the case of producing the synthetic clock from several clocks, the duty cycle of the synthesized clock is below 50%, there can not be the minimum pulse width as a clock and be small the range of permissible input jitter because the duty is gradually high or low according to the number of clock taking part in the synthesis.
Furthermore, since there is a jitter between an external data and the clock inputted from the multi-phase clock generator 101 in the clock selection signal generator 102, the flip flop of the synchronizing circuit and resolving circuit is operated in the state not synchronizing, so that the state of the output value is neither logic "0" nor "1" in the case that a setup time or a hold time between data and clocks are not insured.
At this time, in the case that a metastability occurs in the flip flop of the synchronizing circuit and resolving circuit, it is problematic that a conventional high-speed digital data retiming apparatus fails to generate the clock selection signal.